Analog/Mixed Signal Verilog Modeling Design Engineer

Responsible for developing Digital-Mixed Signal (DMS) models of analog IPs such as touch controller AFEs, wireless power charging, health sensing AFE and satellite AFEs using SystemVerilog language.

Interface with analog design team and chip DV team to develop and support analog/mixed signal models for chip verification.

Understand Verilog-AMS modeling language

Good knowledge of SystemVerilog UDT/UDR nettype (using Cadence wreal or EEnet package)

Familiar with analog circuits such as LDOs, TIAs, analog muxing, SARADC sample-and-hold (S/H), comparators, DAC voltage converter, buffering and amplification, etc....