Opportunity Description
Responsibilities
Support end-to-end physical design implementation activities including floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification for advanced ASIC/SoC platforms used in digital media and broadcast technology environments.
Perform block-level and top-level implementation for high-performance digital processing modules supporting media streaming, video processing, and communication systems.
Drive timing closure activities across multi-corner multi-mode (MCMM) scenarios to achieve performance, power, and area targets.
Analyze and resolve congestion, routing, and signal integrity issues through floorplan optimization and implementation improvements.
Support low-power implementation methodologies including multi-voltage design, leakage optimization, and power-aware verification techniques.
Collaborate closely with cross-functional engineering teams including architecture, RTL, verification, and system integrat...
Support end-to-end physical design implementation activities including floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification for advanced ASIC/SoC platforms used in digital media and broadcast technology environments.
Perform block-level and top-level implementation for high-performance digital processing modules supporting media streaming, video processing, and communication systems.
Drive timing closure activities across multi-corner multi-mode (MCMM) scenarios to achieve performance, power, and area targets.
Analyze and resolve congestion, routing, and signal integrity issues through floorplan optimization and implementation improvements.
Support low-power implementation methodologies including multi-voltage design, leakage optimization, and power-aware verification techniques.
Collaborate closely with cross-functional engineering teams including architecture, RTL, verification, and system integrat...
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