Design Verification Lead Engineer

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Design Verification Lead Engineer

Role Overview:The Lead DV Engineer focuses on the execution and technical management of verification projects. You will lead a focused team to ensure comprehensive test coverage and closure for specific CPU cores or processor blocks.

Key Responsibilities:

+ Technical Execution: Developing and executing detailed verification plans (vPlans) using Cadence vManager.

+ Environment Development: Develop UVM scoreboards, monitors, and complex functional coverage models for multi-protocol or processor-specific interfaces.

+ Debug & Triage: Lead the debug of complex RTL failures and coordinate with design engineers to resolve microarchitectural bugs.

+ Regression Management: Manage automated regression environments (e.g., Jenkins) and ensure targets for code and functional coverage are met.
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