Dft (design for testability) engineer — high-speed automotive serdes socs (3–10 yrs)

20 Gbps) 99% stuck-at, transition, path delay fault coverage)
- Develop and integrate scan insertion flows for large digital subsystems — including full-scan, partial-scan, and scan compression (X-Bounding, EDT, TK-Scan)
- Implement Memory Built-In Self-Test (MBIST) for embedded SRAMs, ROMs, and register files within the So C
- Design and implement Logic BIST (LBIST) infrastructure for in-system and in-field diagnostic test capabilities — critical for automotive functional safety (ISO 26262)
- Develop ATE test programs and ATPG patterns for manufacturing test on Advantest / Teradyne platforms, optimizing for test time and coverage
- Implement IEEE 1687 (i JTAG) network for embedded instrument access and hierarchical test access across complex So C subsystems
- Collaborate with analog design teams to define testability solutions for mixed-signal blocks — including DAC/ADC test modes, PLL characterization modes, and Ser Des loopback
- Partner with physical design tea...