Gate-Level Simulation Analyst

Hi,

Opening for DV with GLS, Bangalore.

JD:-

JD: -Understanding micro architectural details of designs, developing re-usable test bench components 5~7 yrs experience. Creates efficient test plans for RTL validation and Gate level simulations Executing test plans and reporting bugs to drive the development of flawless designs. Responsible for executing RTL verification and GLS activities.

Please share your resume to [email protected]

Regards,

Jaya