20-30M Gross Package for Design and Verification Engineering Role

Mô tả công việc: Nội dung công việc
The work on customer-specific specifications is set to INPUT and the specific design verification work is performed and OUTPUT is performed in the following languages.
Function specifications (English)
- Implementation specifications (English)
- RTL (Verilog)
- Verification strategy book (English)
- Table of verification entries (English)
Build verification environment (SystemVerilog / SVA / UVM / C / C ++)
Script verification (SystemVerilog / SVA / UVM / C / C ++)
Manual verification environment (English)
- Verification results report (in English)
The above can be performed without the assistance of other engineers to some extent

Requirement
- Over 32 years old
- Have strong experience as leader role in some project
* English skill: Intermediate English skills
+ Communication: Intermediate
+Reading: Intermediate - Can read and understand most sentences bu...