ASIC Design Engineer

Chipright

Galway, Galway, Ireland Part Time June 03, 2026

Opportunity Description

Senior Digital Design Engineer We’re looking for a Senior ASIC Digital Design Engineer

Experience required

RTL Design with system Verilog

Linting checks with spyglass

STA

Synthesis

Experience with formal verification would be a plus

Key Qualifications

BS/MS degree with a minimum of 8 years of related experience.

Proficient in scripting languages (Python, Tcl Perl, unix shell)

Familiar with RTL best design practices with SystemVerilog

Familiar with implementation and verification front end flows

Strong communication skills

Part Time Engineers

Submit your application for ASIC Design Engineer at Chipright

Location Galway, Galway

Country Ireland

Type Part Time

Category Engineers

Posted June 03, 2026

Deadline July 13, 2026