Opportunity Description
Job Title: DFT DV Engineer
Location: Santa Clara, CA
Onsite/ Remote: Onsite
Job Description for DFT DV Engineer
The ideal candidate will work with multi-functional global teams to verify IOBIST and JTAG/IJTAG DFT features on our next generation highly complex server processor products. Work in close collaboration with test engineering team to deliver ATE patterns and post silicon bring-up and debug. The ideal candidate will lead verification of high-performance microprocessors. The candidate is able to work with third party IP. You will develop system level and unit level test plans and test benches for verification of high speed D2D interfaces for UCIe hardware. You will write test benches using System Verilog and UVM.
Verify high speed IOBIST interfaces for UCIe test functionality for high performance multi core server class processor.
Create test plans for unit-level and chip-level verification.
Design and implement test benche...
Location: Santa Clara, CA
Onsite/ Remote: Onsite
Job Description for DFT DV Engineer
The ideal candidate will work with multi-functional global teams to verify IOBIST and JTAG/IJTAG DFT features on our next generation highly complex server processor products. Work in close collaboration with test engineering team to deliver ATE patterns and post silicon bring-up and debug. The ideal candidate will lead verification of high-performance microprocessors. The candidate is able to work with third party IP. You will develop system level and unit level test plans and test benches for verification of high speed D2D interfaces for UCIe hardware. You will write test benches using System Verilog and UVM.
Verify high speed IOBIST interfaces for UCIe test functionality for high performance multi core server class processor.
Create test plans for unit-level and chip-level verification.
Design and implement test benche...