Opportunity Description
Skills and Experience Required
Hands on experience in Inserting Scan and generating ATPG vectors for
Stuck-At and At-Speed Faults. In-depth experience in analysing and improving scan coverage
Hands on experience in MBIST (insertion and simulation)
Experience in Boundary Scan, inserting tap controller and P1500
Experience in RTL based and netlist-based insertion flows
Experience in DFT simulation with and without SDF Experience in Synthesis and formal verification tools
Experience in characterization (DC Characteristics)
Experience in generating TDL for ATE and working closely with ATE team during bring-up phase
Good exposure to DFT tools from Mentor, Synopsys and Cadence
Good scripting know-how in Perl and TCL
Experience in Static Timing analysis preferred
Educational Qualification: BE/ME or BTech /MTech