Opportunity Description
DFT Engineer
Experience - 5+years
Location- Bangalore/Hyderabad
Experience with Chip level DFT and Post Silicon debug / analysis
Understanding of DFT architectures like :
- scan chain insertion and verification
- Scan Compression Techniques
- JTAG
a. ATPG Pattern generation
b. ATPG coverage analysis
c. Pattern simulation ( both timing/no timing)
d. Pattern Retargeting
e. Understanding JTAG/IJTAG
f. MBIST and Logic BIST
- Proficient in writing SDC constructs for DFT modes
- Proficient in Python, PERL/Shell script
- Excellent hands-on debug skills and problem-solving attitude.
- Strong Digital design concepts
- Generating scan patterns and coverage statistics for various fault models like :
- stuck at, IDDQ,
- Transition faults, JTAG BSDL,
- pattern generation for Memories (E-fuse etc.)
Experience - 5+years
Location- Bangalore/Hyderabad
Experience with Chip level DFT and Post Silicon debug / analysis
Understanding of DFT architectures like :
- scan chain insertion and verification
- Scan Compression Techniques
- JTAG
a. ATPG Pattern generation
b. ATPG coverage analysis
c. Pattern simulation ( both timing/no timing)
d. Pattern Retargeting
e. Understanding JTAG/IJTAG
f. MBIST and Logic BIST
- Proficient in writing SDC constructs for DFT modes
- Proficient in Python, PERL/Shell script
- Excellent hands-on debug skills and problem-solving attitude.
- Strong Digital design concepts
- Generating scan patterns and coverage statistics for various fault models like :
- stuck at, IDDQ,
- Transition faults, JTAG BSDL,
- pattern generation for Memories (E-fuse etc.)
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