Formal Verification Engineer

Job Summary We are hiring a skilled Formal Verification Engineer with strong expertise in Cadence JasperGold for ASIC/SoC verification projects. The ideal candidate should have hands-on experience in Assertion-Based Verification (ABV) , property checking, and formal verification methodologies for complex digital designs. Key Responsibilities Perform Formal Verification for IP/Sub-system/SoC level designs using Cadence JasperGold. Develop and debug SystemVerilog Assertions (SVA) and formal properties. Execute: Property Verification Connectivity Checks X-Propagation Analysis Deadlock Detection Equivalence Checking Understand RTL architecture and create formal verification plans. Collaborate with RTL, DV, and Architecture teams for verification closure. Analyze counterexamples, debug failures, and identify root causes. Improve design quality through assertion coverage and formal methodologies. Support verification sign-off activities and documentation. Required Skills 4 years of experienc...