Formal verification engineer

Job Summary
We are hiring a skilled Formal Verification Engineer with strong expertise in Cadence Jasper Gold for ASIC/So C verification projects. The ideal candidate should have hands-on experience in Assertion-Based Verification (ABV) , property checking, and formal verification methodologies for complex digital designs.
Key Responsibilities
Perform Formal Verification for IP/Sub-system/So C level designs using Cadence Jasper Gold.
Develop and debug System Verilog Assertions (SVA) and formal properties.
Execute:
Property Verification
Connectivity Checks
X-Propagation Analysis
Deadlock Detection
Equivalence Checking
Understand RTL architecture and create formal verification plans.
Collaborate with RTL, DV, and Architecture teams for verification closure.
Analyze counterexamples, debug failures, and identify root causes.
Improve design quality through assertion coverage and formal methodologies.
Support verification sign-off activities and d...