Opportunity Description
Functional Formal Verification Engineer – Lead
We are seeking an experienced Functional Formal Verification Engineer to join our team and lead formal verification efforts for complex digital designs. As a Lead Formal Verification Engineer, you will play a critical role in ensuring the quality and reliability of our digital designs.
Qualifications:
- Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field.
- 10+ years of experience in formal verification of complex IP/SubSystem/SoCs, with a strong understanding of digital logic design and verification techniques.
- Expertise in formal verification tools and property specification languages (e.g., SVA, PSL), as well as proficiency in HDLs such as System Verilog, Verilog or VHDL.
- Experience with industry-standard EDA formal tools.
- Experience with scripting languages (e.g., Python, Tcl, Perl) and programming languages such as C/C++/SystemC.
...
We are seeking an experienced Functional Formal Verification Engineer to join our team and lead formal verification efforts for complex digital designs. As a Lead Formal Verification Engineer, you will play a critical role in ensuring the quality and reliability of our digital designs.
Qualifications:
- Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field.
- 10+ years of experience in formal verification of complex IP/SubSystem/SoCs, with a strong understanding of digital logic design and verification techniques.
- Expertise in formal verification tools and property specification languages (e.g., SVA, PSL), as well as proficiency in HDLs such as System Verilog, Verilog or VHDL.
- Experience with industry-standard EDA formal tools.
- Experience with scripting languages (e.g., Python, Tcl, Perl) and programming languages such as C/C++/SystemC.
...
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