Opportunity Description
Job Description1. SoC chip integration from RTL to gate level including timing closure
2. Design methodology and integration flow improvement
3. Low power designer
#LI-LL1Requirement1. Experienced in SOC chip integration, sign-off and tapeout
2. Familiar with low power design & architecture
3. Familiar with power calculation
4. Capable of power integrity experience
2. Design methodology and integration flow improvement
3. Low power designer
#LI-LL1Requirement1. Experienced in SOC chip integration, sign-off and tapeout
2. Familiar with low power design & architecture
3. Familiar with power calculation
4. Capable of power integrity experience
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