Immediate hiring for senior rtl design engineers for hyd & blr location

HI All,

We are Hiring Senior RTL design Engineers for HYD & BLR Location.

Exp - 8 to 12 yrs ( BLR Location) & 12+ to 16 yrs ( HYD Location)

Notice Period - Immediate to 30 days.

JD:

8+ years of experience in RTL logic design, verification, synthesis, and timing optimization; Proficient in writing clear, implementable micro-architecture specifications; Expertise in writing efficient RTL code in Verilog and So C integration Good understanding of assertions, coverage analysis, RTL synthesis, and timing closure; Should have worked on interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2 C/I3 C, SPI, SD/SDIO/e MMC, UART, etc. Experience in design bring up and debug on FPGA based emulation platforms like HAPS, Veloce. Fluency with scripting languages (e.g., Perl, Python); Must have gone through at least one tapeout. Preferred: Silicon bring-up and debug experience

Interested candidates, Kindly share with me your updated profile to ana...