Lead RTL Design Engineer for ASIC/SoC

A leading HR management firm in Singapore is seeking an experienced engineer to lead RTL design, simulation, and verification for ASIC/SoC products. Candidates should possess a Master's in Electrical Engineering and a minimum of 5 years of experience in RTL/SoC/digital design. Proficiency in Verilog and SystemVerilog is essential, along with familiarity in collaboration with backend teams. This role provides an exciting opportunity to contribute to cutting-edge technology in a dynamic team environment.
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