LPDDR PHY Design Manager - High‑Speed Memory IO

A leading semiconductor company seeks a candidate to manage the Memory I/O design team in Penang, Malaysia. This role involves defining circuit architecture and designing high-speed analog and digital blocks. Applicants should have strong analytical and communication skills, with at least 5 years of management experience in circuit design or similar. Benefits include standard AMD offerings, and the position emphasizes innovation and collaboration in a diverse team environment.
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