Opportunity Description
A leading technology client based in Barcelona is looking for an experienced UVM / PCIe Verification Engineer for a 6-month contract. The role focuses on developing and maintaining UVM-based verification environments for complex digital designs, specifically ensuring the quality of PCIe interfaces. Candidates should have strong SystemVerilog skills and experience in verification methodologies. The position offers flexible working options, including hybrid and remote arrangements, while being part of an international engineering team.
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