Opportunity Description
Responsibilities
- Work with system engineers on timing requirements and feedback on optimization.
- Work on SoC timing constraint, synthesis and timing closure.
- Work on power structure, eg. isolation of power domains, level‑shifter crossing voltage domains.
- Conduct formal verification for release comparison.
- Support back‑end implementation on timing violation analysis and fix.
- Support scan insertion and optimization.
- Support on power structure and power optimization.
- Bachelor’s or master’s degree in electronic engineering with ASIC design experience.
- Familiar with ASIC design flow.
- Experience in logic synthesis, static timing analysis, timing closure.
- Good understanding of DFT and power structure.
- Familiar with UNIX/Linux environment and scripting.
- Good communication and interpersonal skills.
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