Senior IC Verification Engineer (UVM/SystemVerilog)

Ethos Search Associates Pte Ltd is seeking a verification engineer in Singapore. The role involves developing test plans and environments for IC design and requires a Bachelor's or Master's degree in Electrical or Electronics Engineering along with hands-on experience in Silicon/IP verification using SystemVerilog and UVM. Candidates should possess strong communication and analytical skills, along with familiarity with leading EDA software tools like Cadence and Synopsys.
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