Senior Software Engineer, AEC

Role Overview

The Implementation (RTL to GDSII) Engineer is responsible for the complete physical design execution of ASIC and SoC designs, starting from RTL handoff to final GDSII tape-out. The role includes floorplanning, power planning, placement, clock tree synthesis (CTS), routing, timing closure, physical verification, and signoff across advanced technology nodes. The engineer works closely with RTL, Design Verification, DFT, STA, and signoff teams to meet Power, Performance, Area, Thermal, Schedule (PPATS) targets.

Core Responsibilities (All Levels)

• Execute end-to-end RTL to GDSII physical design flow for block, subsystem, and full-chip designs
• Perform floorplanning, power planning, placement, CTS, and routing
• Drive multi-corner multi-mode (MCMM) static timing analysis and closure
• Ensure physical verification signoff (DRC, LVS, ERC)
• Analyze and close IR drop, EM, and signal integrity issues
• Optimize P...