Opportunity Description
- Has done timing sign-off including timing margin calculations independently on SOC level.
- STA flow enhancement, abstraction with bottleneck identification
- Proficient in design margins and SDC constructs
- TAT reduction in multi-mode, multi power domain/designs
- Generate timing ECOs for Physical design
- Drive ambitious schedules and enables dependent teams to accomplish
- Proficient with EDA tools from Synopsys/Cadence
- Excellent analytical & communication skill
- Show ability to collaborate in multi-functional environment, cross-site or cross-time zone
- Proficient in Tcl and Perl or other scripting relevant language is a plus