Opportunity Description
SoC DFT Engineer
Job Description:
- Scan insertion.
- SCAN DRC/Coverage debug.
- ATPG Pattern generation.
- Gate level simulations ( Zero delay/Timing Delay simulations).
- Worked on JTAG/P1500 protocols.
- Perl/Tcl scripting.
- Timing/Formal verification/PD flow knowledge is plus.
Location: Bangalore
Notice Period: Immediate
Experience: 5+ Years