(Sr./Staff) ISP RTL Design Engineer

Responsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low power consumption Drive ISP Design activities in close collaboration with ISP Algorithm Team
Requirements Minimum MSEE, or BSEE, or equivalent, plus 3+ years of Digital Design and verification related experience Experience / knowledge in CMOS Image Sensor and image signal processing (ISP) Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool. Strong debugging and problem-solving skills Good communication and interpersonal skills Result oriented and embrace change behaviours