Opportunity Description
Job Description
Do design verificationCreate Vplan (checking item)Write test programExecute test programConfirm verification resultGood experience in verification skill set.Experience in Vplan (verification plan) making from TS (target specification)Experience in task pattern (C language, ASM ) from VplanExperience in conduct verification result including coverage judgementFamiliar with simulator/debuger VCS/Verdi/XLM/IndagoKnowledge about SystemVerilog and UVMKnowledge about AMBA protocol: AHB, APB, AXI is a must.Basic knowledge of Formal verification, SVA, TCL.Have knowledge about assembly, C/C++, Verilog languages.Knowledge about Functional Safety, ISO26262 is a plusProvide transparent information, be agile in daily operations.Communicate fluently with teams and customers with a global mindset.Be innovative with excelle...
Full-time
Engineers