Staff RTL Design Engineer - CPU Midcore

Job Description

As a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores, based on the revolutionary open‑source RISC‑V architecture. We are looking for people who are as excited as we are about working in a fast‑paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.

Responsibilities

• Architect, design and implement new features, performance improvements, and ISA extensions in RISC‑V CPU core generators using Chisel.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
• Perform initial sandbox verification, and work with the design verification team to create and execute thorough verif...