TCS Virtual Interview_Design Verification (DV) Engineer

Design Verification (DV) – Job Description Experience Range: 3 to 15 Years Location: Bangalore / Hyderabad / Noida / Ahmedabad/ Chennai/ Mumbai/ Pune Role Overview The Design Verification (DV) Engineer is responsible for ensuring functional correctness, performance, and reliability of ASIC and SoC designs using coverage-driven verification methodologies. The role spans IP, subsystem, and full-chip verification using SystemVerilog/UVM, assertion-based verification, protocol verification, and power-aware simulation, working closely with RTL, Architecture, DFT, PD, and Silicon Validation teams. Core Responsibilities (All Levels) Develop and execute verification plans aligned with design specifications Design and implement UVM-based verification environments and testbenches Create and run directed and constrained-random test cases Analyze simulation results, debug failures, and report root causes Collect and close functional, code, and assertion coverage Collaborate with cross-functional t...