Opportunity Description
Experience
Role and responsibility:
technologies (28nm,16nm,14nm & below ).
including Synthesis, Floor Planning, Power Plan, Integrated Package and
Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis,
complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR
Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC,
ERC, LVS), DFM and DFY and Tapeout.
electrical rules in deepsub micron processes requir...
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