Opportunity Description
* Work with Architecture and Software teams to ensure micro-architecture and design is fully verified/validated across multiple platforms
* Contribute significantly to verification infrastructure development
* Development of System Verilog/UVM based protocol/traffic generators/checkers, development of test plan based on functional requirements
* Contribute significantly to verification infrastructure development
* Development of System Verilog/UVM based protocol/traffic generators/checkers, development of test plan based on functional requirements
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