Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field
7–10 years of hands-on DV experience in semiconductor/ASIC/SoC companies
Deep expertise in SystemVerilog and UVM (Universal Verification Methodology)
Strong understanding of digital design fundamentals — RTL, timing, clocking, resets
Experience with industry-standard simulators: Xcelium, VCS, Questa
Proficiency in coverage-driven verification — functional, code, and toggle coverage
Hands-on experience with formal verification tools and flows
Experience with bus protocols such as AXI, AHB, APB, PCIe, DDR, or similar
Strong debug skills — waveform analysis (Verisium, SimVision)
Familiarity with low-power verification (UPF/CPF) and gls/power-aware gls simulation
 

Core Responsibilities

Strategy and Architecture
Verification Plannin...