Opportunity Description
Principal Substrate and Packaging Engineer
Fully onsite in the San Francisco Bay Area
Full time opportunity
$400-500K total compensation package- base, bonus, stock (depends on skillset/experience level)
Industry leader in semiconductor design focused on advanced IC packaging and high‑speed interconnect technologies. In the role, you will have primarily be responsible for the layout, routing, and functionality of packages and substrates, including design of high-speed lines.
What You’ll Do
- Design and layout advanced IC packages, substrates, and interposers, including high‑speed signal routing
- Collaborate closely with electrical, mechanical, SI/PI, and program teams during front‑end and detailed layout
- Define layout rules, panelization strategies, and stack‑ups with substrate and package vendors
- Perform peer design reviews and contribute to layout bes...
Ready to Apply?
Submit your application for Principal Packaging Engineer at Fidelis Companies
Apply for this Position