Senior FPGA IP & Simulation Lead (Quartus)

754 Altera Semiconductor Technology (M) Sdn. Bhd. is seeking a Senior Technical Lead to guide FPGA IP development and validation within the Altera Quartus Prime ecosystem. This hands-on leadership role requires expertise in RTL design and extensive experience in FPGA tools.

The ideal candidate will have 8-12 years of experience and a strong ability to debug complex issues. Responsibilities include leading design reviews, developing simulation models, and mentoring engineers in best practices.

This position is based in Penang, Malaysia, and supports mentorship and team development.