Senior FPGA Verification Engineer - SystemVerilog/UVM

Epergne Solutions is hiring an FPGA Verification Engineer in Singapore. The role requires 5+ years of experience in FPGA verification, strong knowledge of SystemVerilog and UVM methodologies, and hands-on experience with Ethernet protocols.

The ideal candidate will execute the FPGA verification flow, develop testbenches, perform coverage analysis, and work closely with design teams. A proactive approach to problem solving and scripting skills in TCL, Python, or Perl will be essential.