Senior / Staff Engineer - Mixed Signal Verification

Key responsibilities in your new role

• Contribute to verification in complex projects: understanding requirements, actively supporting the definition & review of the verification plan, setting up verification metrics in digital, developing test cases and ensuring report compliance.
• Responsibilities involve the coordination of verification activities for given projects.
• Apply methodologies (e.g. Universal Verification Methodology (UVM) and System Verilog) and execute tests in these environments on RTL on IP, and Sub-System.
• Create reusable verification components and environments.
• Closely cooperate with analogue and digital designers as well as concept and verification engineers.
• Identify deficiencies in verification methodology and simulation performance, and implement improvements.
• Identify and address synergies between Pre-Silicon Verification methodology and Post-Silicon Validation.

Th...