Opportunity Description
THE ROLE:
This engineer plays a key role in SoC DV flow, he/she will mainly focus on chip level DFX functions verification tasks. Moreover, he/she is expected to collaborate with test engineering team to support DFX silicon bring up and ATE test.
THE PERSON:
Good team worker with solid Verilog RTL design and verification knowledge/experience. Knowledge reservation on System_Verilog/UVM/Modeling/Scan/BIST will be a strong plus.
KEY RESPONSIBILITIES:
- Cutting-edge test strategies study and implementation.
- SoC DFX test plan development based on design specification and DFX feature list.
- Responsible for SoC level DFX test case development and verification.
- Support DFX Cross-die Co-sim simulation and power-aware simulation tasks.
- Support DFX silicon bring up and ATE test.
PREFERRED EXPERIENCE:
- Solid background on process, device or ASIC design.
- Strong te...