Sr. Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Responsibilities :

+ Design Verification for interconnect IP and Tensilica Processor subsystems.

+ Relevant experience in interconnect and subsystems is strongly preferred

+ Crafting verification plans and executing on those plans to verify highly complex and configurable designs.

+ Responsible for coverage collection and closure

+ Work closely with cross functional teams (DV/Arch/Design/FW) to identify coverage scope

+ Responsible for creating / working with UVM based DV environment.


Required Skills and Experience:

+ 10+ years of design verification experience

+ BS (or higher) in EE/Computer Engineering

+ Strong technical and interpersonal skills

+ Excellent knowledge of Interconnects, NoCs and design verification fundamentals.

+ Excellent knowledge and command...