Opportunity Description
NVIDIA is looking for best-in-class STA (Static Timing analysis) Physical Design Engineers to join our outstanding Networking DFT team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
+ DFT STA execution, from rtl driven constraints and definitions through DFT constraints quality assurance to STA sign-off.
+ Be part of a unique team of experts who have deep understanding in all aspects of pre and post silicon.
+ Be exposed and work on a variety of challenging designs, unique DFT solutions that require deep silicon implementation understanding.
+ Daily work involves all aspects of static timing analysis - constraints, environmen...
What you will be doing:
+ DFT STA execution, from rtl driven constraints and definitions through DFT constraints quality assurance to STA sign-off.
+ Be part of a unique team of experts who have deep understanding in all aspects of pre and post silicon.
+ Be exposed and work on a variety of challenging designs, unique DFT solutions that require deep silicon implementation understanding.
+ Daily work involves all aspects of static timing analysis - constraints, environmen...