Staff Physical Design Engineer – Top-Level Timing & STA

We are looking for a Senior/Staff STA Engineer to lead full-chip timing signoff activities for cutting-edge SoCs at advanced technology nodes (5nm / 3nm / 2nm).

The candidate should possess deep expertise in MMMC timing closure, hierarchical timing budgeting, ECO convergence, and final tapeout signoff.

This role requires close collaboration with RTL, Physical Design, Clocking, to achieve timing closure for high-performance silicon.

Key Responsibilities

• Own full-chip STA across all modes and PVT corners.
• Drive MMMC timing closure and convergence.
• Develop and maintain timing constraints and hierarchical timing budgets.
• Analyze setup/hold violations and drive ECO closure.
• Execute timing signoff using industry-standard tools.
• Collaborate with Physical Design and Clock teams to improve timing QoR.
• Debug complex timing issues at top-level integration.
• Improve signoff methodolo...