Synthesis & STA Engineer — RTL Timing & Low-Power

ByteDance in Singapore is looking for an experienced IC Design Engineer to join their Silicon Platform Team. The role involves performing logic synthesis, timing signoff, and low-power design techniques to optimize designs for productions. Candidates should have at least 3 years of relevant experience, proficiency in Verilog/SystemVerilog, as well as familiarity with various EDA tools. This is an opportunity to work closely with both front-end and back-end engineers in a collaborative environment.
#J-18808-Ljbffr