Opportunity Description
TPU PCIe RTL Design Engineer
_corporate_fare_ Google _place_ Sunnyvale, CA, USA
**Mid**
Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.
**Minimum qualifications:**
+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
+ 5 years of experience in ASIC design, including one project focused on PCIe logic.
+ Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl.
+ Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition.
+ Experience with PCIe protocol layers (e.g., Transaction, Data Link, and Physical) or LTSSM.
+ Experience with Clock Domain Crossing (CDC), timing closure, or synthesis flows.
**Preferred qualifications:**
+ Master's degree or PhD in Electrical Engineer...
_corporate_fare_ Google _place_ Sunnyvale, CA, USA
**Mid**
Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.
**Minimum qualifications:**
+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
+ 5 years of experience in ASIC design, including one project focused on PCIe logic.
+ Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl.
+ Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition.
+ Experience with PCIe protocol layers (e.g., Transaction, Data Link, and Physical) or LTSSM.
+ Experience with Clock Domain Crossing (CDC), timing closure, or synthesis flows.
**Preferred qualifications:**
+ Master's degree or PhD in Electrical Engineer...
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